I. Field of the Invention
The present invention relates to communications. More particularly, the present invention relates to a novel and improved receiver comprising a sigma-delta analog-to-digital converter.
II. Description of the Related Art
In many modern communication systems, digital transmission is utilized because of the improved efficiency and the ability to detect and correct transmission errors. Exemplary digital transmission formats include binary phase shift keying (BPSK), quaternary phase shift keying (QPSK), offset quaternary phase shift keying (OQPSK), m-ary phase shift keying (m-PSK), and quadrature amplitude modulation (QAM). Exemplary communication systems which utilize digital transmission include code division multiple access (CDMA) communication systems and high definition television (HDTV) systems. The use of CDMA techniques in a multiple access communication system is disclosed in U.S. Pat. No. 4,901,307, entitled "SPREAD SPECTRUM MULTIPLE ACCESS COMMUNICATION SYSTEM USING SATELLITE OR TERRESTRIAL REPEATERS", and U.S. Pat. No. 5,103,459, entitled "SYSTEM AND METHOD FOR GENERATING WAVEFORMS IN A CDMA CELLULAR TELEPHONE SYSTEM", both assigned to the assignee of the present invention and incorporated by reference herein. An exemplary HDTV system is disclosed in U.S. Pat. No. 5,452,104, U.S. Pat. No. 5,107,345, and U.S. Pat. No. 5,021,891, all three entitled "ADAPTIVE BLOCK SIZE IMAGE COMPRESSION METHOD AND SYSTEM", and U.S. Pat. No. 5,576,767, entitled "INTERFRAME VIDEO ENCODING AND DECODING SYSTEM", all four patents are assigned to the assignee of the present invention and incorporated by reference herein.
In the CDMA system, a base station communicates with one or more remote stations. The base station is typically located at a fixed location. Therefore, power consumption is less important consideration in the design of the base station. The remote stations are typically consumer units which exist in high quantity. Therefore, cost and reliability are important design considerations because of the number of units produced. Furthermore, in some applications such as a CDMA mobile communication system, power consumption is critical because of the portable nature of the remote station. Tradeoffs between performance, cost, and power consumption are usually made in the design of the remote stations.
In digital transmission, the digitized data is used to modulate a carrier sinusoid using one of the formats listed above. The modulated waveform is further processed (e.g. filtered, amplified, and upconverted) and transmitted to the remote station. At the remote station, the transmitted RF signal is received and demodulated by a receiver.
A block diagram of an exemplary super-heterodyne receiver 2100 of the prior art which is used for quadrature demodulation of QSPK, OQPSK, and QAM signal is illustrated in FIG. 1. Receiver 2100 can be used at the base station or the remote station. Within receiver 2100, the transmitted RF signal is received by antenna 2112, routed through duplexer 2114, and provided to front end 2102. Within front end 2102, amplifier (AMP) 2116 amplifies the signal and provides the signal to bandpass filter 2118 which filters the signal to remove undesired signals. As used in this specification, undesired signals comprise noise, spurious signals, undesirable images, interference, and jammers. The filtered RF signal is provided to mixer 2120 which downconverts the signal to a fixed intermediate frequency (IF) with the sinusoid from local oscillator (LO1) 2122. The IF signal from mixer 2120 is filtered by bandpass filter 2124 and amplified by automatic gain control (AGC) amplifier 2126 to produce the required signal amplitude at the input of analog-to-digital-converters (ADCs) 2140. The gain controlled signal is provided to demodulator 2104. Within demodulator 2104, two mixers 2128a and 2128b downconvert the signal into the baseband I and Q signals with the sinusoid provided by local oscillator (LO2) 2134 and phase shifter 2136, respectively. The baseband I and Q signals are provided to lowpass filters 2130a and 2130b, respectively, which provide match filtering, adjacent channel rejection, and/or anti-alias filtering of the baseband signals. The filtered signals are provided to ADCs 2140a and 2140b which sample the signals to produce the digitized baseband samples. The samples are provided to baseband processor 2150 for further processing (e.g. error detection, error correction, and decompression) to produce reconstructed estimates of the transmitted data.
The first frequency downconversion with mixer 2120 allows receiver 2100 to downconvert signals at various RF frequencies to a fixed IF frequency where more signal processing can be performed. The fixed IF frequency allows bandpass filter 2124 to be implemented as a fixed bandpass filter, such as a surface acoustic wave (SAW) filter, to remove undesired signals from the IF signal. Removal of undesired signals is important since these signals can fold into the signal band (e.g. the band where the input signal is present) at the second frequency downconversion stage. Furthermore, the undesired signals can significantly increase the amplitude of the signal into various active components, such as the amplifiers and mixers, which can cause higher level of intermodulation products from the non-linearity in the active components. Undesired signals and intermodulation products can cause degradation in the performance of the communication system.
The quadrature demodulator of the prior art has several major drawbacks. First, the required filtering by bandpass filter 2124 and/or lowpass filters 2130 can be complex. These filters may require a flat passband, high attenuation in the stopband, and sharp roll-off in the transition band. These filters are implemented with analog circuits. Component tolerance of analog circuits is difficult to maintain and can cause distortion in the frequency response of these filters. The performance of receiver 2100 can be degraded as the result of the distortion. Second, quadrature balance is difficult to maintain over many production units because of component tolerance in phase splitter 2136, mixers 2128, lowpass filter 2130, and ADCs 2140. Any mismatch in the two signal paths results in quadrature imbalance and degradation in the performance of receiver 2100. Path mismatch results in cross-talk of the I signal onto the Q signal, and vice versa. The cross-talk signal behaves as additive noise in the desired signal and results in poor detection of the desired signal. Third, the prior art receiver architecture has DC offset because the analog filters are at baseband. And fourth, ADCs 2140 can cause degradation in the performance of receiver 2100 for various reasons described below.
In most demodulators, one or more ADCs are required to convert an analog waveform in continuous time into discrete samples at evenly spaced time intervals. Some important performance parameters of an ADC include dynamic range, linearity, and DC offset. Each of these parameters can affect the performance of the communication system. Dynamic range can affect the bit-error-rate (BER) performance of the receiver because the noise from the ADC degrades the ability of the ADC to properly detect the input signal. Linearity relates to the difference between an actual transfer curve (e.g. digital output versus analog input) and the ideal transfer curve. Good linearity is more difficult to obtain as the number of bits in the ADC increases. Poor linearity can degrade the error detection/correction process. And DC offset can degrade the performance of the phase locked loop in the receiver and of the error correcting decoder, such as the Viterbi decoder.
In the prior art, flash ADCs or successive approximation ADCs are used to sample the baseband signals. Within the flash ADC, the input signal is divided by a resistive ladder to produce L-1 comparison signals, where L=2.sup.m and m is the number of bits in the ADC. The comparison signals are compared against L-1 reference voltages, which are generated by a second resistive ladder, by L-1 comparators. Flash ADCs are bulky and consume high power because L-1 comparators and 2L resistors are required. Flash ADCs can have poor linearity and poor DC offset characteristics if the resistors in the resistive ladder are not matched. However, flash ADCs are popular because of their high operating speed.
Successive approximation ADCs are also popular for communication systems. These ADCs minimize complexity by performing approximations of the input signal over two or more stages. However, these ADCs can also exhibit poor linearity and poor DC offset characteristics similar to those of the flash ADCs. Thus, flash ADCs and successive approximation ADCs are not ideal candidates for use in many communication applications.
Sigma delta analog-to-digital converters (.SIGMA..DELTA. ADCs) have better performance than flash and successive approximation ADCs because of the inherent architecture of the .SIGMA..DELTA. ADC. .SIGMA..DELTA. ADC performs analog-to-digital conversion of the input signal by making successive one-bit approximations of the input signal at a sampling frequency which is many times higher than the bandwidth of the input signal. The output samples comprise the input signal and the quantization noise. However, the .SIGMA..DELTA. ADC can be designed such that the quantization noise in the signal band (e.g. the band where the signal is present) is pushed to out-of-band frequency (or noise shaped) where filtering is more easily performed. The out-of-band quantization noise is normally not an additional concern because filtering is typically provided in communication devices to remove undesired signals, such as jammers.
.SIGMA..DELTA. ADC can provide high dynamic range, good linearity, and low DC offset because of the inherent structure of the .SIGMA..DELTA. ADC. For example, high dynamic range can be obtained by selecting a sufficient oversampling ratio (OSR) and the proper noise shaping filter characteristic. For bandpass sampling, the oversampling ratio is defined as the sampling frequency divided by the two-sided bandwidth of the input. Additionally, good linearity can be obtained because of the simple one-bit quantizer within the .SIGMA..DELTA. ADC. For bandpass sampling.SIGMA..DELTA. ADC, DC offset is still present but is located away from the desired signal.
Because a high oversampling ratio is required for high performance, .SIGMA..DELTA. ADCs have been traditionally limited to applications where the input signal is a low bandwidth signal, such as audio application. However, with the advent of high speed analog circuits, .SIGMA..DELTA. ADCs can be implemented to operate at high speed. High speed bandpass and baseband .SIGMA..DELTA. ADC designs and implementations are disclosed in detail in copending U.S. patent application Ser. No. 08/928,874 entitled "BANDPASS SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER", filed Sep. 12, 1997, assigned to the assignee of the present invention and incorporated by reference herein.